Cache memory has long been used in data processing systems to decrease the memory access time for the central processing unit (CPU) thereof. A cache memory is typically a relatively high speed, relatively small memory in which active portions of a program and/or data are placed. The cache memory is typically faster than main memory by a factor of five to ten and typically approaches the speed of the CPU itself. By keeping the most frequently accessed instructions and/or data in the high speed cache memory, the average memory access time will approach the access time of the cache.
The active program instructions and data may be kept in a cache memory by utilizing the phenomena known as "locality of reference". The locality of reference phenomena recognizes that most computer program instruction processing proceeds in a sequential fashion with multiple loops, and with the CPU repeatedly referring to a set of instructions in a particular localized area of memory. Thus, loops and subroutines tend to localize the references to memory for fetching instructions. Similarly, memory references to data also tend to be localized, because table look-up routines or other iterative routines typically repeatedly refer to a small portion of memory.
In view of the phenomena of locality of reference, a small, high speed cache memory may be provided for storing a block of memory containing data and/or instructions which are presently being processed. Although the cache is only a small fraction of the size of main memory, a large fraction of memory requests over a given period of time will be found in the cache memory because of the locality of reference property of programs.
In a CPU which has a relatively small, relatively high speed cache memory and a relatively large, relatively low speed main memory, the CPU examines the cache when a memory access instruction is processed. If the desired word is found in cache, it is read from the cache. If the word is not found in cache, the main memory is accessed to read that word, and a block of words containing that word is transferred from main memory to cache memory. Accordingly, future references to memory are likely to find the required words in the cache memory because of the locality of reference property.
The performance of cache memory is frequently measured in terms of a "hit ratio". When the CPU refers to memory and finds the word in cache, it produces a "hit". If the word is not found in cache, then it is in main memory and it counts as a "miss". The ratio of the number of hits divided by the total CPU references to memory (i.e. hits plus misses) is the hit ratio. Experimental data obtained by running representative programs has indicated that hit ratios of 0.9 (90%) and higher may be obtained. With such high hit ratios, the memory access time of the overall data processing system approaches the memory access time of the cache memory, and may improve the memory access time of main memory by a factor of five to ten or more. Accordingly, the average memory access time of the data processing system can be improved considerably by the use of a cache.
Data processing systems are typically used to perform many independent tasks. When a task is first begun, the hit ratio of the cache is typically low because the instructions and/or data to be performed will not be found in the cache. Such a cache is known as a "cold" cache. Then, as processing of a task continues, more and more of the instructions and/or data which are needed may be found in the cache. The cache is then referred to as a "warm" cache because the hit ratio becomes very high.
In order to maximize the hit ratio, many data processing system architectures allow system control over the use of the cache. For example, the cache may be controlled to store instructions only, data only, or both instructions and data. Similarly, the cache may be controlled to lock a particular line or page in the cache, without allowing overwrites. The design and operation of cache memory in a data processing architecture is described in detail in Chapter 12 of the textbook entitled "Computer System Architecture" by Mano, Prentice-Hall (Second Edition, 1982).
Cache memory is often used in high speed data processing system architectures which also often include multiple interrupt levels. As is well known to those having skill in the art, an interrupt may be an "external" interrupt, for example from a keyboard, disk drive, or other peripheral unit, or may be an "internal" interrupt from an internally generated timer. Upon occurrence of an interrupt, a first (interrupted) task being performed in the data processing system is suspended and a second (interrupting) task is performed. The interrupted task may be resumed after completion of the interrupting task.
High performance data processing architectures often allow multiple virtual machines to perform independent tasks, with multiple interrupt levels available for each of the virtual machines. A Processor Status Word (PSW) is typically stored in the central processing unit to track the status of the processor, including the interrupt level in which the processor is operating. For complex data processing systems, a Processor Status Vector (PSV), comprising a plurality of processor status words, is typically used to track multiple priority interrupt levels.
In a multiple interrupt level virtual machine environment, a new processor status vector is typically loaded into a set of processor status registers when a new virtual machine begins processing. See, for example, U.S. Pat. No. 4,001,783 to Monahan et al., entitled Priority Interrupt Mechanism, which describes a high performance data processor using a cache memory and having eight levels of interrupts with a complete set of registers for each of the eight levels. When an interrupt causes the initiation of a new process, the current process is left intact in the registers assigned to that process level. Control may then be returned to the interrupted process simply by reactivating that process level. The need to store and restore register information concerning the interrupted processes is thereby eliminated, along with the accompanying overhead.
A similar system is described in U.S. Pat. No. 4,028,664 to Monahan et al., entitled Apparatus For Data of the Highest Priority Process Having the Highest Priority Channel to a Processor. Similarly, U.S. Pat. No. 4,823,256 to Bishop et al., entitled Reconfigurable Dual Processor System, describes a dual processor system using a cache memory for high speed memory operations. Each processor's hardware state is indicated by the contents of a program status word that stores software related information associated with the currently executing program.
Yet another example of a high performance virtual machine data processing architecture that uses a cache memory and multiple interrupt levels is described in U.S. Pat. No. 4,635,186 to Oman et al. entitled Detection and Correction of Multi-Chip Synchronization Errors, and assigned to the assignee of the present invention. In this patent, a high speed cache memory is used, and the interrupt level is controlled using a program status vector comprising a set of eight program status words for each virtual machine.
In summary, high speed cache memory and multiple interrupt levels are among the many features used to enhance the performance of a data processing system. When properly designed, the cache allows memory access at speeds approaching that of the central processing unit, even though most of the data and instructions are stored in lower speed main memory. When properly designed, multiple level interrupt systems allow ongoing processing to be interrupted on an as needed basis, to perform higher priority tasks. Multiple interrupt levels may also be used in a virtual machine environment, with each virtual machine including multiple levels of interrupts associated therewith. Accordingly, there is a continued need to improve the performance and operation of cache memory and interrupt handling in data processing system.